勤益科大機構典藏:Item 987654321/2327
English  |  正體中文  |  简体中文  |  Items with full text/Total items : 2928/5721 (51%)
Visitors : 373873      Online Users : 460
RC Version 6.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
    •  Adv. Search
    Home ‧ Login ‧ Upload ‧ Help ‧ About ‧ Administer Goto mobile version


    Please use this identifier to cite or link to this item: http://ir.lib.ncut.edu.tw/handle/987654321/2327


    Title: 互補式高性能加法器核心電路之設計
    Design of High Performance Complementary Mode Adder Cores
    Authors: 董秋溝;謝韶徽;黃國興;邱雯姿
    Contributors: 電子工程系
    Department of Electronic Engineering
    Keywords: 加法器;算數運算;電子系統
    Date: 2003-12
    Issue Date: 2008-12-23 10:26:51 (UTC+8)
    Publisher: 勤益科技大學
    Abstract: 本論文提出四種全新隱藏輸出驅動能力的全加器核心電路，並以此全加器核心電路建構三個新的高性能加法器電路模組。經由SPICE與TSMC 0.35μm 2P4M混合模式製程技術模擬結果，證明我們提出的M3加法器電路模組平均每位元由11個電晶體組成，比其他具有輸出驅動能力之全加器減少45%~58%MOS電晶體數，M2加法器電路模組則比其他全加器電路減少了48%~80%的必v消耗。
    Relation: 勤益學報 21(2) p.189-196
    Appears in Collections:[National CHIN-YI University of Technology] 勤益學報

    Files in This Item:

    File SizeFormat
    0KbUnknown1839View/Open


    All items in NCUTIR are protected by copyright, with all rights reserved.

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback