Totally Self-Checking Carry-Select Adder Design Based on Two-Rail Code

Please use this identifier to cite or link to this item: http://ir.lib.ncut.edu.tw/handle/987654321/3518

Title:	Totally Self-Checking Carry-Select Adder Design Based on Two-Rail Code
Authors:	Shao-Hui Shieh Ming-En Lee
Contributors:	勤益科技大學
Keywords:	Totally self-checking two-rail code carry select adder checker on-line test
Date:	2010-06
Issue Date:	2010-09-16 17:02:30 (UTC+8)
Abstract:	In this paper, the totally self-checking (TSC) carry-select adder (CSA) design is proposed. The capability of TSC can detect all single stuck-at faults on-line in normal operation mode. The proposed CSA has not only self-checking capability but also educed transistor count. The design is based on TSMC 0.18um process technology, and a real chip is implemented. The transistor count of roposed totally self-checking CSA design is less than conventional CSA, and even reduced 34.85% compared with [4] for thirty-two bits design. The reduced ratio of transistor-count is proportional to the bit count of totally self-checking CSA to be designed. Our design has other advantages such as high extensibility, non-tree detector structure, and thus having reasonable propagation delay time and can keeping well normal operation in the high-bit design.
Relation:	第五屆智慧生活科技研討會論文集(上)
Appears in Collections:	[Department of Computer Science and Information Engineering] The 5th Imtelligent Living Technology Conference

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