Totally self-checking (TSC) adder design based on the Berger code is proposed for embedded adder cores. A self-checking circuit can execute on-line testing in normal system operation. TSC can immediately detect the error of an electronic system
or a computer to avoid the data damaged or the malfunction of a function circuit. Hence, TSC can enhance the reliability of an electronic system, i.e., using TSC may reduce the harm of the electronic system to the lowest as we wish. A real silicon
implementation is given based on the TSMC 0.35μm mixed signal process technology. The experiment results show that transistor count of the proposed checker bits generator (CBG_New) has 59.3% reduced than that of previous MOS design and the power consumption is also reduced to 4.83mW under
the condition of the operating frequency at 100 MHz.The lower power is due to eliminating both the charge and discharge times of the weight decoder circuit in our design.
