Low-Power high-speed full adder for portable electronic applications

勤益科大機構典藏 > 電資學院 > 電子工程系(所) > 【電子工程系所】期刊論文 > Item 987654321/6103

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題名:	Low-Power high-speed full adder for portable electronic applications
作者:	董秋溝
貢獻者:	電子工程(學)系
日期:	2013-08
上傳時間:	2017-09-28 09:31:38 (UTC+8)
摘要:	A low-power, high-speed full adder (FA), abbreviated as LPHS-FA, is presented as an elegant way to reduce circuit complexity and improve the performance thereof. Employing as few as 15 MOSFETs in total, an LPHS-FA requires 60-73% fewer transistors than other existing FAs with drivability. For validation purpose, HSPICE simulations are conducted on all the proposed and referenced FAs based on the TSMC 0.18-μm CMOS process technology. The LPHS-FA is found to provide a 20.4-21.2% power saving, a 12.3-67.0% delay time reduction and a 35-102% reduction in power delay product compared with the referenced FAs. In short, an LPHS-FA is presented in a concise form as a high-performance FA in practical applications. © The Institution of Engineering and Technology 2013. (6 refs)
關聯:	ELECTRONICS LETTERS
顯示於類別:	[電子工程系(所)] 【電子工程系所】期刊論文

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