Network Packet Engine on an SOC platform through a Field Programmable Gate Array

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Title:	Network Packet Engine on an SOC platform through a Field Programmable Gate Array
Authors:	林灶生
Contributors:	資訊工程系
Date:	2009-04
Issue Date:	2017-10-13 09:31:24 (UTC+8)
Abstract:	A number of software-based routers are available for experimental or commercial uses by employing either a generic PC with an operating system or embedded processor unit integrated with Media Access Controller (MAC). Software-based solutions lead to performance problems and high cost to manufacture a system; on the other hand, all functions that are implemented with hardware increases the complexity and loses flexibility. In this paper, a Network Packet Engine (NPE) is proposed in an SOC (System On a Chip) platform on a FPGA (Field Programmable Gate Array) based chip. In the proposed NPE, infrastructure components and a packet engine module implemented by hardware architecture are ported into an SOC system. Our approach is to identify the common features that are required for hardware, and leave a small amount of implementations to software. This not only will make the processor less complex and thus cost down, but also will reduce hardware complexity. The proposed NPE application shows a real parallel architecture that has benefits in comparison to sequential machines. In the experimental results, a promising performance can be obtained in the proposed NPE and can be applied in real networks. (14 refs)
Relation:	Int. J. of Electrical Engineering
Appears in Collections:	[Department of Computer Science and Information Engineering] 【資訊工程系所】期刊論文

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