Time-interleaved CMOS chip design of Manchester and Miller encoder for RFID application

勤益科大機構典藏 > 電資學院 > 電子工程系(所) > 【電子工程系所】期刊論文 > Item 987654321/7097

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题名:	Time-interleaved CMOS chip design of Manchester and Miller encoder for RFID application
作者:	洪玉城
贡献者:	電子工程(學)系
日期:	2012-03
上传时间:	2018-01-07 14:26:06 (UTC+8)
摘要:	In this paper, we propose a modified Manchester and Miller encoder that can operate in high frequency without a sophisticated circuit structure. Based on the previous proposed architecture, the study has adopted the concept of parallel operation to improve data throughput. In addition, the technique of hardware sharing is adopted in this design to reduce the number of transistors. This circuit is realized by using TSMC CMOS 0.35-μm 2P4M technologies. The simulation results of HSPICE indicate that it functions and works successfully at 200-MHz data rate. An experimental chip had been fabricated and measured. The measured results show that the experimental chip has 50 MHz data throughput rate under 3.3-V supply voltage. The lowest supply voltage 0.6 V is achievable working at 5 kHz data rate. The average power consumption of the circuit under room temperature is 549 μW. The chip area is 70.7 μm × 72.2 μm. The compact structure and high-speed operation are useful for radio frequency identification applications.
關聯:	Analog Integrated Circuits and Signal Processing
显示于类别:	[電子工程系(所)] 【電子工程系所】期刊論文

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