In this paper, the totally self-checking (TSC) carry-select adder (CSA) design is proposed. The capability of TSC can detect all single stuck-at faults on-line in normal operation mode. The proposed CSA has not only self-checking capability but also educed
transistor count. The design is based on TSMC
0.18um process technology, and a real chip is
implemented. The transistor count of roposed totally self-checking CSA design is less than conventional CSA, and even reduced 34.85% compared with [4] for thirty-two bits design. The reduced ratio of transistor-count is proportional to the bit count of
totally self-checking CSA to be designed. Our design has other advantages such as high extensibility, non-tree detector structure, and thus having reasonable propagation delay time and can keeping well normal operation in the high-bit design.
