In this paper, we propose a modified Manchester and Miller encoder that can operate in high frequency without a sophisticated circuit structure. Based on the previous proposed architecture, the study has adopted the concept of parallel operation to improve data throughput. In addition, the technique of hardware sharing is adopted in this design to reduce the number of transistors. This circuit is realized by using TSMC CMOS 0.35-μm 2P4M technologies. The simulation results of HSPICE indicate that it functions and works successfully at 200-MHz data rate. An experimental chip had been fabricated and measured. The measured results show that the experimental chip has 50 MHz data throughput rate under 3.3-V supply voltage. The lowest supply voltage 0.6 V is achievable working at 5 kHz data rate. The average power consumption of the circuit under room temperature is 549 μW. The chip area is 70.7 μm × 72.2 μm. The compact structure and high-speed operation are useful for radio frequency identification applications.
