A New Delay-Line Sharing Based CMOS Digital PWM Circuit

NCUTIR > College of Electrical Engineering and Computer Science > Department of Electronic Engineering > 【電子工程系所】期刊論文 > Item 987654321/7098

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Title:	A New Delay-Line Sharing Based CMOS Digital PWM Circuit
Authors:	洪玉城
Contributors:	電子工程(學)系
Date:	2012-10
Issue Date:	2018-01-07 14:27:31 (UTC+8)
Abstract:	This paper presents a new circuit design for digital pulse-width modulators (DPWM). This method improves the structure of hybrid DPWM to a more compact architecture by utilizing the separation of MSB (most significant bit) and LSB (least significant bit) groups. In addition, a delay-line function block is shared with MSB and LSB groups to reduce power consumption. HSPICE post-layout simulation shows that this new DPWM circuit operates successfully at 200 MHz clock frequency and has 1.55-mW power consumption. An experimental chip had been fabricated by using a standard 0.18 micron CMOS process. The layout area of the chip including I/O pads is 461 μm×370 μm. The new DPWM design carries the advantages of smaller chip area and low power consumption especially for the high resolution required. (13 refs)
Relation:	International Journal of Advancements in computing Technology
Appears in Collections:	[Department of Electronic Engineering] 【電子工程系所】期刊論文

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