A New Delay-Line Sharing Based CMOS Digital PWM Circuit

勤益科大機構典藏 > 電資學院 > 電子工程系(所) > 【電子工程系所】期刊論文 > Item 987654321/7098

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题名:	A New Delay-Line Sharing Based CMOS Digital PWM Circuit
作者:	洪玉城
贡献者:	電子工程(學)系
日期:	2012-10
上传时间:	2018-01-07 14:27:31 (UTC+8)
摘要:	This paper presents a new circuit design for digital pulse-width modulators (DPWM). This method improves the structure of hybrid DPWM to a more compact architecture by utilizing the separation of MSB (most significant bit) and LSB (least significant bit) groups. In addition, a delay-line function block is shared with MSB and LSB groups to reduce power consumption. HSPICE post-layout simulation shows that this new DPWM circuit operates successfully at 200 MHz clock frequency and has 1.55-mW power consumption. An experimental chip had been fabricated by using a standard 0.18 micron CMOS process. The layout area of the chip including I/O pads is 461 μm×370 μm. The new DPWM design carries the advantages of smaller chip area and low power consumption especially for the high resolution required. (13 refs)
關聯:	International Journal of Advancements in computing Technology
显示于类别:	[電子工程系(所)] 【電子工程系所】期刊論文

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